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Ordering number : ENA0979
LA72702NV
Monolithic Linear IC
LA72702NV
Overview
The LA72702NV is a US TV BTSC Decoder.
For US TV
BTSC Decoder
Features
* With SIF circuit, alignment-free* STEREO channel separation. * When base band signal input, separation is adjusted by input level. * Dual slave address(80h, 84h).
Functions
* SIF FM-Demodulator * STEREO detection * STEREO decoder * STEREO detection sensitivity change function * dbx Noise Reduction * SAP demodulator * SAP detection * SAP output select 2-levels * SAP detection sensitivity change function
Specifications
Maximum Ratings at Ta = 25C
Parameter Maximum power supply voltage Allowable power dissipation Operating temperature Storage temperature Symbol VCCH max Pd max Topr Tstg Ta85C, Mounted on a specified board* Conditions Ratings 7.0 290 -20 to +85 -55 to +150 Unit V mW C C
* Mounted on a specified board: 114.3mmx76.1mmx1.6mm, glass epoxy board
Operating Conditions at Ta = 25C
Parameter Recommended operating voltage Allowable operating voltage range Symbol vacate VCCH op Conditions Ratings 5.0 4.5 to 5.5 Unit V V
Any and all SANYO Semiconductor Co.,Ltd. products described or contained herein are, with regard to "standard application", intended for the use as general electronics equipment (home appliances, AV equipment, communication device, office equipment, industrial equipment etc.). The products mentioned herein shall not be intended for use for any "special application" (medical equipment whose purpose is to sustain life, aerospace instrument, nuclear control device, burning appliances, transportation machine, traffic signal system, safety equipment etc.) that shall require extremely high level of reliability and can directly threaten human lives in case of failure or malfunction of the product or may cause harm to human bodies, nor shall they grant any guarantee thereof. If you should intend to use our products for applications outside the standard applications of our customer who is considering such use and/or outside the scope of our intended standard applications, please consult with us prior to the intended use. If there is no consultation or inquiry before the intended use, our customer shall be solely responsible for the use. Specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein stipulate the performance, characteristics, and functions of the described products in the independent state, and are not guarantees of the performance, characteristics, and functions of the described products as mounted in the customer's products or equipment. To verify symptoms and states that cannot be evaluated in an independent device, the customer should always evaluate and test devices mounted in the customer's products or equipment.
N2807 TI IM 20070112-S00005 No.A0979-1/10
LA72702NV
Electrical Characteristics at Ta = 25C, VDD = 5.0V
Parameter Current dissipation SIF input level (Reference) Symbol ICC VILIM Conditions min No signal Inflow current at pin 19, default condition fc = 4.5MHz Deviation MONO (300Hz, Mod = 100%, Pre-emphasis ON) 25kHz Base band input level (Reference) VILIMB 100% Modulation MONO(L+R) : 530mVp-p (300Hz, Pre-emphasis ON) SUB(L-R) SAP MONO output level MONO distortion MONO frequency characteristics MONO S/N ratio STEREO output level STEREO distortion STEREO frequency characteristics STEREO S/N ratio STEREO separation 1 STEREO separation 2 STEREO Detection level-1 VOMON THDMON FCM1 SNM VOST THDS FCS1 SNS STSE1 STSE2 VINSD1 : 380mVp-p (300Hz, dbx-NR ON), Pilot : 110mVp-p : 300mVp-p (300Hz, dbx-NR ON) -7.0 -5.5 0.15 -2 55 -7.0 0 65 -5.5 0.5 -2 50 20 20 30 0 60 25 25 38 45 -4.5 1.0 2 -4.5 0.6 2 dBV % dB dB dBV % dB dB dB dB % 30 (80) Ratings typ 40 (90) max 50 (100) mA dBV Unit
fm=1kHz, 100% Mod, 15kHz LPF fm=1kHz, 100% Mod, 15kHz LPF fm=3kHz, 30% Mod, Pre-emphasis ON * Measure ratio from fm=1kHz level. S=VOMON, N=0% Mod, 15kHz LPF fm=1kHz, 100% Mod, 15kHz LPF fm=1kHz, 100% Mod, 15kHz LPF fm=3kHz, 30% Mod, 15kHz LPF * Measure ratio from fm=1kHz level. S=VOST, N=0% Mod, 15kHz LPF f=300Hz (R/L), 30% Mod, 15kHz LPF f=3kHz (R/L), 30% Mod, 15kHz LPF Except Stereo Detection * Measure pilot level. Stereo Detection
* Serial control "SENS HI" Pilot (fH)=15.73kHz STEREO Detection level-2 STEREO Detection hysteresis SAP output level-1 SAP output level-2 SAP distortion SAP S/N ratio SAP detection level-1 VINSD2 HYST VOSA1 VOSA2 THDSA SNSA VINSA1 Except Stereo Detection * Serial control "SENS LO" Input Mod. Difference at Stereo/Except Stereo Det. * Serial control "SENS HI" fm=1kHz, 100% Mod, 15kHz LPF * SAP-1 (serial control) fm=1kHz, 100% Mod, 15kHz LPF * SAP-2 (serial control) fm=1kHz, 100% Mod, 15kHz LPF S=VOSA2, N=0% Mod, 15kHz LPF Except SAP SAP Det. * Serial control "SENS HI" SAP Carrier=5fH only * Measure output level. SAP detection level-2 VINSA2 Except SAP SAP Det. * Serial control "SENS LO" * Measure output level. SAP detection hysteresis HYSA Input Mod. Difference at SAP/Except SAP Det. * SAP carrier only. * Serial control "SENS HI" MODE output MONO MODE output SAP MODE output STEREO MODE output ST + SAP Stereo detect speed (Reference ) MODMO MODSA MODST MODSS STDT Input=MONO : f=1kHz, 0% Mod Input=SAP : Carrier Input=STEREO : Pilot Input=STEREO : Pilot, SAP : Carrier Input=STEREO : Pilot I2C data no-send Measure pin 20 voltage change to 2.8V timing from Power ON SAP detect speed (Reference ) SAPDT SAP : Carrier I2C data no-send Measure pin 20 voltage change to 1.9V timing from Power ON * Normally measurement condition is Input = SIF mode (90dBV) * " Reference " Items are reference levels, their specs are no-guarantee. (350) (1000) ms 0.7 1.6 2.5 3.5 1 1.9 2.8 3.8 (480) 1.3 2.2 3.1 4.2 (1000) V V V V ms 2 5 10 % 17 24 31 % 50 10 0.7 60 17 24 1.5 % dB % -7.5 -5.5 -3.5 dBV -14.0 -11.0 -8.0 dBV 10 20 30 % Stereo Detection 38 47 53 %
No.A0979-2/10
LA72702NV
Package Dimensions
unit : mm (typ) 3175C
7.8 24 13
5.6
7.6
1 0.65 (0.33) 0.22
12 0.15
SANYO : SSOP24(275mil)
Mode Condition
I2C data in Signal D8 Stereo + SAP (0) FIX D7 (0) SIF (1) BASE band D6 0 1 0 1 Stereo Mono + SAP 0 1 0 1 MONO * : no care D5 (0) STEREO SENS Lo (1) Hi D4 (0) SAP SENS Lo (1) Hi 1 1 1 0 0 0 1 1 1 0 0 0 0 0 0 1 1 0 0 1 0 0 1 1 0 0 0 1 1 1 0 0 1 1 0 1 0 1 0 1 0 0 1 0 1 0 1 1 0 0 1 0 1 0 1 L+R L+R L+R Off L L L L+R L+R L+R Off L+R SAP SAP L+R L+R Off L+R L+R L+R Off L+R L+R L+R Off R R R L+R L+R L+R Off L+R SAP SAP SAP SAP Off L+R L+R L+R Off F-MONO F-MONO F-MONO MUTE Stereo Stereo Stereo F-MONO F-MONO F-MONO MUTE MONO SAP-1 SAP-2 MULTI-1 MULTI-2 MUTE MONO MONO MONO MUTE 0 0 1.0V 0 1 1.9V 1 0 2.8V D3 0 0 0 0 0 D2 0 0 0 1 1 D1 0 1 1 0 0 Lch pin18 L SAP SAP L+R L+R Rch pin17 R SAP SAP SAP SAP Mode condition Stereo SAP-1 SAP-2 MULTI-1 MULTI-2 D8 1 D7 1 Mode pin20 3.8V Output mode I2C out
0.1
(1.3)
1.5max
0.5
No.A0979-3/10
LA72702NV
I C Control Table
Grp-1 (Normally use : group-1 only)
D8 * D7 D6 D5 D4 D3 D2 0 0 1 1 * 0 1 * 0 1 * 0 1 * 0 1 * 0 1 * 0 1 * : Shows Initial condition D1 0 1 0 1 Condition Stereo SAP Both MUTE Normal (Auto DET) Forced Mono SAP SENS LO SAP SENS HI Stereo SENS LO Stereo SENS HI SAP Level-1 SAP Level-2 SIF mode Base Band mode Fix Prohibit (TEST MODE)
2
Read out data
D8 D7 D6 0 0 1 0 1 D5 0 D4 0 D3 0 D2 0 D1 0 Condition Fixed Normal SAP det Normal Stereo det
Test mode condition(Reference) When STOP condition transform at Grp-1 data-end, controlled NORMAL mode. Grp-2 is only test condition. Usually, these data are no-need. Their data are no guarantee, except all L condition.
D8 0 D7 0 D6 0 D5 0 D4 0 0 0 0 0 0 0 0 1 1 1 1 1 1 1 1 Blank Bits are no-care D3 0 0 0 0 1 1 1 1 0 0 0 0 1 1 1 1 D2 0 0 1 1 0 0 1 1 0 0 1 1 0 0 1 1 D1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 0 1 Condition/Monitor position Normal (Usually, Fixed) TEST-1 SIF output TEST-2 SAP BPF TEST-3 (reserved) TEST-4 ST VCO TEST-5 (reserved) TEST-6 SAP monitor TEST-7 ST monitor TEST-8 Pilot cancel monitor TEST-9 dbx 2.19k LPF TEST-10 dbx 408 LPF TEST-11 dbx DET 10k LPF TEST-12 dbx SPEC 7.6k LPF TEST-13 dbx SPEC output TEST-14 L+R/lL-R monitor TEST-15 dbx 2.09k LPF
Slave addresses are 80h (1000 000*, at pin8 Open/GND) and 84h (1000 010*, at pin8 H).
No.A0979-4/10
MODE Monitor out OUT(L) OUT(R) VCC 5V 100F 4.7F + 15 14 13 + + 22F 4.7F 1F + 47F 20 MODE OUT MUTE MATRIX REGULATOR
Spectral In Offset Cancel Wide RMS DET
1F 0.1F 1F + 23 22 21 19 18 17 16 2.2F + + 10F 10F 4.7F + + + 0.1F 0.033F 0.033F
+
4.7k
24
Block Diagram and Application
L+R -6dB LPF MUTE L-R DEMOD ST/SAP SW LPF SAP DEMOD SAP DET LPF SAP BPF Address GND L-R/SAP
PILOT LEVEL DET PILOT CANCELLER
dbx processor
STEREO PLL
Offset Cancell Control SYSTEM CONTROL ST SAP
Spectral DET
LA72702NV
SIF DEMOD
I2C DECODE
1 4.7F + 0.1F 4.5M BPF 1F to 0.33F
2
3
4
5
6
7 *560k 0.1F
8
9
10
11
12
1F +
2.2F Address Control I2C DATA I2C CLOCK
22F +
*: SAP Sensitivity only pin7. Resistor remove.
SIF SIGNAL from Tuner
SLAVE ADDRESS = 80h (1000 000 *) : Pin8 = OPEN/GND SLAVE ADDRESS = 84h (1000 010 *) : Pin8 = H
Spectral RMS DET
PILOT DET
No.A0979-5/10
LA72702NV
Pin Functions
Pin No. 1 Pin Name PCPLDET Function Pilot level detect for stero detection DC: voltage AC: level DC : 2.4V Equivalent Circuit
40k 1
40k
1k
160k
2 PC_DC_IN AC coupling (Input) DC : 2.4V AC : 2.4Vp-p
3
PC_DCOUT
AC coupling (Output)
DC : 2.4V AC : 2.4Vp-p
500
3
2
1k
4
PC FIL
SIF offset cancel
DC : 2.6V
1k 4
1k
5
PISIF
Signal input Common input at SIF, Base band
DC : 3.7V
10k
5
500 1k
6 7
GND CSAPDET SAP carrier level detect for SAP detection DC : 2.8V
70k 1k 1k 7 2k 1k
8
ADDSEL
Slave address change control OPEN/GND : 80h 5V : 84h
DC : 0V
8 1k 100k
Continued on next page.
No.A0979-6/10
LA72702NV
Continued from preceding page. Pin No. 9 Pin Name SDA Serial data input Function DC: voltage AC: level Equivalent Circuit
5V
9 1k
0V
10 SCL Serial clock input
5V
10 1k
0V
11 PC DBXIN Offset cancel feedback filter DC: 2.4V
11
5k
12
PCDETSPE
Spectral band RMS detect
DC: 2.3V
1k 200
12
13 PCTIMSPE dbx spectral detect DC: 2.4V
13
5k
14
PCTNWID
Wide band RMS detect
DC: 2.4V
1k 200
14
15 PCSPECIN dbx main signal V/I convert filter DC: 2.4V
10k
15
16
PC KE6B
Offset cancel feedback filter
DC: 2.4V AC: 220mVp-p
250 500 16 500
Continued on next page.
No.A0979-7/10
LA72702NV
Continued from preceding page. Pin No. 17 Pin Name PORCH Line out R Function DC: voltage AC: level DC: 2.4V AC: 1.4Vp-p Equivalent Circuit
50k 300 50k 300 17
18
POLCH
Line out L
DC: 2.4V AC: 1.4Vp-p
50k 300 50k 300 18
19 20
VCC POLED Mode out MONO SAP STEREO = 0.9V = 2.0V = 3.0V DC: See Right AC: Test only
20
STEREO + SAP = 3.8V
1k
21
PCREG
Reference voltage
DC: 2.4V
10k 9.6k 1k 21
500
22
PMAINOUT
Offset cancel feedback filter
DC: 1.6V
450k 22
500
23
PCPLC
Pilot level detect for pilot canceller
DC: 2.4V
40k
40k
1k
160k 23
Continued on next page.
No.A0979-8/10
LA72702NV
Continued from preceding page. Pin No. 24 Pin Name PCPTFILT Function Pilot level detect for ST PLL filter DC: voltage AC: level DC: 2.4V Equivalent Circuit
40k
40k
1k
160k 24
I2C BUS Serial Interface Specification
(1) Data transfer manual This IC adopts control method (I2C-BUS) with serial data, and controlled by two terminals which called SCL (serial clock) and SDA (serial data).At first, set up*1 the condition of starting data transfer, and after that, input 8 bit data to SDA terminal with synchronized SCL terminal clock. The order of transferring is first, MSB (the Most Scale of Bit), and save the order. The 9th bit takes ACK (Acknowledge) period, during SCL terminal takes `H', this IC pull down the SDA terminal. After transferred the necessary data, two terminals lead to set up and of *2 data transfer stop condition, thus the transfer comes to close. *1 Defined by SCL rise down SDA during `H' period. *2 Defined by SCL rise up SDA during `H' period. (2) Transfer data format After transfer start condition, transfers slave address (1000 000*) to SDA terminal, control data, then, stop condition (See figure 1). Slave address is made up of 7bits, *38th bit shows the direction of transferring data, if it is `L' takes write mode (As this IC side, this is input operation mode), and in case of `H' reading mode (As this IC side, this is output operation mode). Data works with all of bit, transfer the stop condition before stop 8bit transfer, and to stop transfer, it will be canceled the transfer dates. *3 It is called R/W bit. Fig.1 DATA STRUCTURE "WRITE" mode
START Condition Slave Address R/W L ACK Control data ACK STOP condition
Fig.2 DATA STRUCTURE "READ" mode
START condition Slave Address R/W H ACK Internal Data * ACK STOP condition
The output data synchronizes with the clock of SCL pin. Then, the ACK output is made after the output data. bit8 is result of STERO DET (H : STEREO) bit7 is result of SAP DET (H : SAP) bit6 to bit1 are fixed to `L' (3) Initialize This IC is initialized for circuit protection. Initial condition is "0 (All bits) ".
No.A0979-9/10
LA72702NV
Reference
Parameter LOW level input voltage HIGH level input voltage LOW level output current SCL clock frequency Set-up time for a repeated START condition Hold time START condition. After this period, the first clock pulse is generated LOW period of the SCL clock Rise time of both SDA and SDL signals HIGH period of the SCL clock Fall time of both SDA and SDL signals Data hold time Data set-up time Set-up time for STOP condition BUS free time between a STOP and START condition Symbol VIL VIH IOL fSCL tSU : STA tHD : STA tLOW tR tHIGH tF tHD : DAT tSU : DAT tSU : STO tBUF 0 4.7 4.0 4.7 0 4.0 0 0 250 4.0 4.7 1.0 1.0 min -0.5 2.5 max 1.5 5.5 3.0 100 unit V V mA kHz s s s s s s s ns s s
Definition of timing
tR t HI G H tF
S CL
t HD : S TA t SU : S TA t LO W t HD : D AT A t SU : D AT t SU : S TO t BU F
S DA
SANYO Semiconductor Co.,Ltd. assumes no responsibility for equipment failures that result from using products at values that exceed, even momentarily, rated values (such as maximum ratings, operating condition ranges, or other parameters) listed in products specifications of any and all SANYO Semiconductor Co.,Ltd. products described or contained herein. SANYO Semiconductor Co.,Ltd. strives to supply high-quality high-reliability products, however, any and all semiconductor products fail or malfunction with some probability. It is possible that these probabilistic failures or malfunction could give rise to accidents or events that could endanger human lives, trouble that could give rise to smoke or fire, or accidents that could cause damage to other property. When designing equipment, adopt safety measures so that these kinds of accidents or events cannot occur. Such measures include but are not limited to protective circuits and error prevention circuits for safe design, redundant design, and structural design. In the event that any or all SANYO Semiconductor Co.,Ltd. products described or contained herein are controlled under any of applicable local export control laws and regulations, such products may require the export license from the authorities concerned in accordance with the above law. No part of this publication may be reproduced or transmitted in any form or by any means, electronic or mechanical, including photocopying and recording, or any information storage or retrieval system, or otherwise, without the prior written consent of SANYO Semiconductor Co.,Ltd. Any and all information described or contained herein are subject to change without notice due to product/technology improvement, etc. When designing equipment, refer to the "Delivery Specification" for the SANYO Semiconductor Co.,Ltd. product that you intend to use. Information (including circuit diagrams and circuit parameters) herein is for example only; it is not guaranteed for volume production. Upon using the technical information or products described herein, neither warranty nor license shall be granted with regard to intellectual property rights or any other rights of SANYO Semiconductor Co.,Ltd. or any third party. SANYO Semiconductor Co.,Ltd. shall not be liable for any claim or suits with regard to a third party's intellectual property rights which has resulted from the use of the technical information and products mentioned above.
This catalog provides information as of November, 2007. Specifications and information herein are subject to change without notice.
PS No.A0979-10/10

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